TSMC announces 6nm process

N6, TSMC’s terminology for the 6nm process, will have three advantages, according to CEO CC Wei, speaking at the company’s latest quarterly results announcement last week. N6 will have design rules that are 100% compatible with N7, allowing customers to directly migrate from N7, he said. In addition, N6 will increase logic density by 18% from N7 and provide a highly competitive performance-to-cost advantage. Finally, N6 will offer shortened cycle time and reduced defect density.

“The numbers N6 and N5 look pretty close, but actually the performance — they still have a big gap,” Wei said. “N5 compared with N7, actually, the logic density increases by 80%. N6 compared with N7 is only 18%.”

N5 will deliver a significant jump in density and performance, but it will also be a full node upgrade. Unlike N6, it will require customers to design products from the ground up.

Risk production of N6 is scheduled for the first quarter next year with volume production starting before the end of 2020, according to TSMC.


Hardware enthusiast and webdesigner, has over 20 years of experience in the I.T world, has worked with sales, tech support and webdesign . Jonathan@365hardwarenews.com

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