The Gen-Z Consortium, an organization developing an open standard interconnect designed to provide high-speed, low latency, memory-semantic access to data and devices, today shared the Gen-Z Core Specification 1.0 is publicly available on its website. The Gen-Z Core Specification 1.0 enables silicon providers and IP developers to begin the development of products enabling Gen-Z technology solutions. Gen-Z’s memory-centric standards-based approach focuses on providing an Open, reliable, flexible, secure, and high performance architecture for housing and analyzing the incredible amount of information at the edge coming into the data center.
“Our membership has grown significantly throughout 2017, now totaling more than fifty members, and we are proud of the hard work that has culminated with the release of our first Core Specification,” said Gen-Z President, Kurtis Bowman. “We anticipate great things in 2018 as silicon developers begin implementing Gen-Z technology into their offerings and the ecosystem continues to grow.”
Gen-Z technology supports a wide range of new storage class memory media and acceleration devices, features new hybrid and memory-centric computing technologies, and uses a highly efficient, performance-optimized solution stack. Its memory media independence and high bandwidth coupled with low latency enables advanced workloads and technologies for end-to-end secure connectivity from node level to rack scale.
Learn more and download the Gen-Z Core Specification 1.0 on our website.